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Research Fellow in Digital Design for Advanced Communication Systems

Department of Electrical & Electronic Engineering

Location:  Guildford
Salary:  £31,866 to £40,322 per annum
Fixed Term
Post Type:  Full Time
Advert Placed:  Friday 15 November 2019
Closing Date:  Sunday 15 December 2019
Reference:  090219

The Institute for Communication Systems (ICS) home of the 5G Innovation Centre (5GIC) is looking to recruit a research fellow in Digital Design for Advanced Communication Systems. The successfulcandidate will be part of the Wireless Systems Lab and will have the opportunity to work very close with our industrial partners as well as with academic partners all over the world.

The successful candidate will be part of a group that focuses on advanced signal processing architectures for future communication systems and their efficient realization on hardware platforms (i.e., algorithmic architectural co-design), as well as on experimentation and concept validation via software defined radios. The post holder will be expected to design, develop and validate efficient architectures for current and future communication systems, mainly targeting physical layer functionality on Field-Programmable Gate Arrays. Displaying a high degree of autonomy, the successful candidate will find novel solutions to complex problems, as defined by standardisation committees and the Wireless Systems Group.

ICS is the largest academic research institute in Europe specialising on all aspects of ICT (Information and Communication Technologies). It is home to over 200 researchers with expertise in all communication and broadcasting systems and has developed the best in class large scale testbeds for research and innovation and enjoys the state of the art lab and computing facilities.

5GIC established in 2012, is the world’s first dedicated centre in researching end-to-end aspects of 5G and works closely with national and international leading academic institutes and key industrial partners.

The post holder must have expertise in the following:

  • Development of advanced physical layer digital signal processing algorithms targeting high throughput and low-latencyon embedded platforms,preferably on Xilinx FPGAsusing RTL and/orHLS(e.g., Xilinx System Generator for DSP).

The post holder must also have at least one of the following:

  • Good understanding of signal processing for wireless communication systems
  • Recent experience in the development of advanced physical layer algorithms (e.g., forward error correction)
  • Track record of publications in highly ranked journals and conferences in at least one of the above fields

It would be desirable but not essential for the post holder to also have:

  • An overall working knowledge of cellular networks (e.g.,: LTE, 5GNR).
  • Experience on x86 multiprocessingand SIMD optimisation.
  • C/C++ or Python and Linux shell scripting experience.
  • Experience with a high-speed FPGA protocol, e.g., PCIe or 10GE.
  • Prior experience with wireless research platforms (e.g., USRPs, WARPs).

For informal enquiries please contact: Dr Konstantinos Nikitopoulos (k.nikitopoulos@surrey.ac.uk)

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Please note, it is University Policy to offer a starting salary equivalent to Level 3.6 (£31,866) to successful applicants who have been awarded, but are yet to receive, their PhD certificate.  Once the original PhD certificate has been submitted to the local HR Department, the salary will be increased to Level 4.1 (£32,817).


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